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PCI CD/CDa Configurable DMA Interface User’s Guide Registers

EDT, Inc. May 2007 19

Table 4. Configuration Space Status Field Values

Table 5. Configuration Space Command Field Values

PCI Local Bus Addresses

Figure 6 describes the PCI CD/CDa interface registers in detail. The addresses listed in Figure 6 are

offsets from the gate array boot ROM base addresses. This base address is initialized by the PCI Local

Bus host operating system at boot time.

NOTE The addresses 0x80 and 0x84 are used by the pciload utility to update the gate array. User

applications must not modify use these registers. Results of running pciload do not take effect until

after the board has been turned off and then on again.

Bit Name Value Bit Name Value

0–4 reserved 0 10 DEVSEL Timing 0

5 66 MHz Capable 1 11 Signaled Target Abort implemented

6 UDF Supported 0 12 Received Target Abort implemented

7 Fast Back-to-back Capable 0 13 Received Master Abort implemented

8 Data Parity Error Detected implemented 14 Signaled System Error implemented

9 DEVSEL Timing 1 15 Detected Parity Error implemented

Bit Name Value Bit Name Value

0 IO Space 0 6 Parity Error Response implemented

1 Memory Space implemented 7 Wait Cycle Control 0

2 Bus Master implemented 8 SERR# Enable implemented

3 Special Cycles 0 9 Fast Back-to-back Enable implemented

4 Memory Write and

Invalidate Enable

0 10–15 reserved 0

5 VGA Palette Snoop 0

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 39 40

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CDA CD 60 Betriebsanweisung Seite 23