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Registers PCI CD/CDa Configurable DMA Interface User’s Guide

34 EDT, Inc. May 2007

PCI CDa Registers

The following four registers apply to the PCI CDa only.

PLL Programming Register

Size 8-bit

I/O read-write

Address 0x20

Access EDT_SS_PLL_CTL

Comment The program

set_ss_vco uses this register to program the serial interface of the

PLL.

PLL Divider Register

Size 16-bit

I/O read-only

Address 0x24, 0x25

Access EDT_SS_PLL0_CLK,

Comment The program

set_ss_vco sets this register, which is a post-scalar divider used to

achieve lower frequencies than those to which you can program the PLL directly.

After this division, the clocks are divided by two to even the duty cycle. To enable

the PLL circuit, set bit 7 in the Funct Register.

Output Data Valid Delay Register

Size 8-bit

I/O read-write

Address 0x28

Access ODV_DELAY

Bit Name Description

7 PLL_SCLK Connected to the PLL serial clock input.

6 PLL_DATA Connected to the PLL serial data input.

5–4 not used

3–0 PLL_STROBE Connected to the strobe inputs of the PLL .

Bit Description

15–0 Programmable post-scalar divider to set PLL frequency.

Bit Description

7–0 Set the number of 16-bit words by which to delay output. The specified number of outgoing words

accumulate in the FIFO, reducing or eliminating ODV transitioning on startup.

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CDA CD 60 Betriebsanweisung Seite 38