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PCI CD/CDa Configurable DMA Interface User’s Guide Registers
EDT, Inc. May 2007 33
Interface Configuration Register
Size 8-bit
I/O read-write
Address 0x0F
Access PCD_CONFIG
Figure 8 shows the structure of a 32-bit data word, with no swapping in effect. With SHORTSWAP set,
short 0 appears before short 1. With BYTESWAP set, byte 2 appears before byte 3, and byte 0 before
byte 1. With both set, byte 0 appears first, followed by byte 1, byte 2, and finally byte 3.
Figure 8. Data Word Structure Without Swapping
Bit PCD_ Description
7 SETIDV Set input data valid (used for debugging).
6 PIOEN Enables programmed I/O. A value of 1 translates DMA channel
buffers and enables the Programmed I/O Low Register and the
Programmed I/O High Register. Write the desired 16-bit word, the
low eight bits first to the Programmed I/O Low Register, and then the
high eight bits to the Programmed I/O High Register. When the
Programmed I/O High Register is written to, the firmware generates
an ODV pulse in mid-clock, to enable the device to latch the data.
5 SETDNR Set this bit to stop transfer to the device, as if the device had set DNR.
4 DED Disable output delay. If set, may cause ODV transitioning on DMA
start and underflows.
3 SHORTSWAP Set to 1 if the host computer writes the first 16-bit word on bits 16–31
of the PCI data bus (bigendian format) instead of bits 0–15 as defined
in the PCI Bus specification. See Figure 8 for the details of data word
structure.
2 SETAV64 PCI CDa only: For debugging. Set to tell PCI Xilinx that data is always
available.
PCI CD: not used
1 SELRXT PCI CDa only: Set to select RXT as the source for TXT and SENDT.
(See Table 1 on page 14 for descriptions of these signals.)
PCI CD: not used
0 BYTESWAP A value of 1 swaps the order of bytes in a 16-bit word of data coming
in from the data source. See Figure 8 for the details of data word
structure.
short 1 short 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
byte 3 byte 2 byte 1 byte 0
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