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Registers PCI CD/CDa Configurable DMA Interface User’s Guide

24 EDT, Inc. May 2007

29 DMA_START Write a 1 to this bit to indicate that the values of this register and the SG DMA Next

Address register are valid; this sets this bit to 0, indicating either that the copy is in

progress, or that the device is waiting for the current DMA to complete. In either case,

this register and the SG DMA Next Address register are not available for writing.

Reading a value of 1 indicates that the SG DMA Next Count and SG DMA Next Address

registers have been copied into the SG DMA Current Count and SG DMA Current

Address registers and that the Next Count and Next Address registers are once more

available for writing.

28 EN_MN_DONE A value of 1 enables the main DMA page done interrupt (bit 18).

27 EN_SG_DONE Enable scatter-gather DMA done interrupt. A value of 1 enables DMA_DONE (bit 30

of this register) to set DMA_INT (bit 12 of the Stat Register on page 30), thus causing

an interrupt if the PCI_EN_INTR bit is set (bit 15 of the PCI Interrupt and UI Xilinx

Configuration Register).

A value of 0 disables the DMA_DONE from causing an interrupt.

26 DMA_ABORT A value of 1 stops the DMA transfer in progress and cancels the next one, clearing bits

29 and 30. Always 0 when read.

25 DMA_MEM_RD A value of 1 specifies a read operation; 0 specifies write.

24 BURST_EN A value of 0 means bytes are written to memory as soon as they are received. A value

of 1 means bytes are saved to write the most efficient number at once.

23 MN_DMA_DONE Read only: a value of 1 indicates that the main DMA is not active.

22 MN_NXT_EMP Read only: a value of 1 indicates that the main DMA next address and next count

registers are empty.

21–19 Reserved for EDT internal use.

18 PG_INT Read-only: a value of 1 indicates that the page interrupt is set (enabled by bit 28 of this

page interrupt bit) was set in the scatter-gather DMA list (see Figure 7). If the PCI

interrupt is enabled (bit 15 of the PCI Interrupt and UI Xilinx Configuration Register), this

bit causes a PCI interrupt.

Clear this bit by disabling the page done interrupt (bit 28 of this register).

17 CURPG_INT Read-only: a value of 1 indicates that bit 16, the page interrupt bit, was set in the

scatter-gather DMA list entry for the current main DMA page.

16 NXTPG_INT Read-only: a value of 1 indicates that bit 16, the page interrupt bit, was set in the

scatter-gather DMA list entry for the next main DMA page.

15–0

The number of bytes in the next scatter-gather DMA list.

Bit EDT_ Description

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 39 40

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CDA CD 60 Betriebsanweisung Seite 28