CDA CD 60 Betriebsanweisung PDF herunterladen (Seite 33)

PCI CD/CDa Configurable DMA Interface User’s Guide Registers

EDT, Inc. May 2007 29

Data Path Status Register

Size 8-bit

I/O read-only

Address 0x01

Access PCD_DATA_PATH_STAT

Funct Register

Size 8-bit

I/O read-write

Address 0x02

Access PCD_FUNCT

Bit PCD_ Description

7 IDV Reflects IDV state. (PCI CD only — spare on PCI CDa)

6 INFFAFULL If set, input FIFO is almost full.

4–5 INFFULL If set, input FIFO is full.

3 OVERFLOW This bit is asserted when the input FIFO is full and the IDV signal is high. Reset this

bit with the ENABLE bit in the Command Register on page 28.

2 UNDERFLOW If the DNR signal is low and the ODV signal goes low because the output FIFO runs

out of data, then this bit is asserted and remains so throughout the data transfer.

Reset this bit with the ENABLE bit in the command register.

1 IF_NOT_EMP If this bit is set, the input FIFO is not empty.

0 OF_NOT_EMP If this bit is set, the output FIFO is not empty.

Bit PCD_ Description

7 PLLCLK Set to enable the PLL circuit; see the PLL Divider Register for the use

of this bit. Applies to the PCI CDa, and to the PCI CD running

pcd_src.bit only.

6 SELAV PCI CD only: used to program the PLL and select the clock.

PCI CDa: not used

5 FREQ7 PCI CD only: used to program the PLL and select the clock.

PCI CDa: not used

4 FREQ6 PCI CD only: used to program the PLL and select the clock.

PCI CDa: not used

0–3 FUNCT Sets the state of the user-definable FUNCT outputs.

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CDA CD 60 Betriebsanweisung Seite 33