CDA CD 60 Spezifikationen PDF herunterladen (Seite 14)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 14

FIFO Flushing

First-in, first-out (FIFO) memory buffers are used to smooth data transmission between different types

of data sinks internal to PCI DV boards. For instance, the FIFO stores information processed by the

user interface Xilinx until the PCI Xilinx retrieves it across the PCI bus. The PCI bus normally sends

information in bursts, so the FIFO allows this same information to be sent smoothly.

When acquiring or sending data, you should flush the FIFO immediately before performing DMA. This

also resets the FIFO to an empty state. The following subroutines either flush the FIFO or set it to flush

automatically at the start of DMA. Complete descriptions are available on page 38.

void edt_flush_fifo (EDTDev *edt_p)

This routine flushes the global board FIFO. It is called just before the first call to

edt_start_buffers. It affects all channels on a multi-channel board. See

edt_flush_channel for per-channel FIFO flushing. Use caution when calling edt_flush_fifo

immediately before edt_read or edt_write, because there is a delay allocating kernel DMA resources

during thich the FIFO may overflow with data. See edt_set_firstflush below.

int edt_set_firstflush (EDTDev *edt_p, int flag)

This routine performs a global FIFO flush just before DMA starts in the driver when the flag is

nonzero. This routine is useful when using edt_read and edt_write. The default setting is OFF.

void edt_flush_channel (EDTDev *edt_p)

This routine flushes only the DMA channel associated with edt_p. It requires firmware support from

the user interface Xilinx and is not implemented on all firmware configurations.

void pcd_pio_flush_fifo (EDTDev *edt_p)

After calling pcd_pio_init(EdtDev *edt_p), this routine may be used to flush the global board FIFO by

using memory-mapped register access instead of using a system call to the driver. This method is

slightly faster.

Multi-Threaded Programming

EDT recognizes there are many ways to write multi-threaded programs that work, so the following

guidelines are provided to help with your initial programming efforts or as a means of troubleshooting

applications that use EDT boards.

The EDT driver is thread-safe with the following constraints:

1. All DMA operations must be performed in the same thread as edt_open and edt_close with respect

to each channel. Other threads may open the same channel concurrently with DMA, but should

perform no DMA-related operations. This is because kernel DMA resources are allocated on a per-

thread basis and must be allocated and released in the same thread.

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CDA CD 60 Spezifikationen Seite 14