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PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 63

Signals

The hardware flow control protocol assumes that FIFO or memory buffers on both ends implement

almost-full and almost-empty thresholds. Therefore, when a “not ready to accept data” signal is sent to

the transmitting device, the receiver can still accommodate enough data to allow for cable delay and

synchronization.

Signal PCI CD I/O Description

DAT(15:0) I/O Sixteen bi-directional data lines for DMA data.

STAT(3:0) I Four general-purpose control inputs. Any can be enabled to

interrupt the PCI bus host.

FUNCT(3:0) O Four general-purpose program control outputs. Can be used to

reset the user device or indicate DMA direction for bi-directional

devices.

SENDT O Send Timing is a constant clock driven by the DMA interface

that can be used by the user device to generate the receive

timing. This signal does not hae to be used. The PCI CD-20

outputs a 10 MHz clock. The PCI CD-40 outputs a 20 MHz

clock.

RXT I Receive Timing is an input to the DMA device. When the

pcd_looped.bit configuration is used, the RXT signal frequency

must be generated by the external device. When the pcd_src.bit

is used, the RXT signal must be looped back from the SENDT

signal. It is best, although not required, that this signal is a

continuous clock. Data clocked into the DMA interface must

propagate through pipelining registers before it can be

transferred into PCI bus memory. If the RXT clock stops, data is

left in this pipe instead of being transferred to host memory.

TXT O Transmit Timing is an output from the DMA interface. TXT

synchronizes the DMA output data and control signals. TXT is

either internally generated from the same source as SENDT, or

looped back from RXT.

IDV I Input Data Valid is asserted by the device synchronous with

RXT, to tell the DMA interface that data on the DATA(15:0)

signals are valid and must be registered and transferred to the

PCI bus memory. The DMA interface will accomplish this unless

the BNR signal has been asserted for >32 IDV signals.

BNR O Bus Not Ready is asserted by the DMA interface synchronous

with TXT when 32 bytes or fewer of data space remains for input

data from the device. This warns you to stop the data transfer or

prepare for overflow.

ODV O Output Data Valid is asserted by the DMA interface when it has

placed valid output data on DATA(15:0). ODV is asserted

synchronously with the TXT clock, and only if the DNR signal is

not asserted.

DNR I Device Not Ready is asserted by the device synchronous with

the RXT clock when the user device is about to run out of space

for storing data from the DMA interface. The amount of overrun

buffer required in the device varies according to the cable

length. The PCI CD may produce four or more words of valid

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