CDA CD 60 Spezifikationen PDF herunterladen (Seite 78)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 78

Scatter-gather DMA Next Count and Control Register

Size 32-bit

I/O read-write

Address 0x1C

Access EDT_SG_NXT_CNT

Comments The driver software writes this register as described in step 2 of the list in the

Performing DMA section on page 74.

Bit EDT_ Description

D31 EN_RDY Enable scatter-gather next empty interrupt. A value of 1

enables DMA_START (bit 29 of this register) to set

DMA_INT (bit 12 of the Status register), thus causing an

interrupt if the PCI_EN_INTR bit is set (bit 15 of the Main

DMA Command and Configuration register).

A value of 0 disables the DMA_START from causing an

interrupt.

D30 DMA_DONE Read-only: a value of 0 indicates that a scatter-gather DMA

transfer is currently in progress. A value of 1 indicates that

the current scatter-gather DMA is complete.

D29 DMA_START Write a 1 to this bit to indicate that the values of this

this sets this bit to 0, indicating either that the copy is in

progress, or that the device is waiting for the current DMA

to complete. In either case, this register and the SG DMA

Next Address register are not available for writing.

Reading a value of 1 indicates that the SG DMA Next

Count and SG DMA Next Address registers have been

copied into the SG DMA Current Count and SG DMA

Current Address registers and that the Next Count and

Next Address registers are once more available for writing.

D28 EN_MN_DONE A value of 1 enables the main DMA page done interrupt (bit

18).

D27 EN_SG_DONE Enable scatter-gather DMA done interrupt. A value of 1

enables DMA_DONE (bit 30 of this register) to set

DMA_INT (bit 12 of the Status register), thus causing an

interrupt if the PCI_EN_INTR bit is set (bit 15 of the Main

DMA Command and Configuration register).

A value of 0 disables the DMA_DONE from causing an

interrupt.

D26 DMA_ABORT

A value of 1 stops the DMA transfer in progress and

cancels the next one, clearing bits 29 and 30. Always 0

when read.

D25 DMA_MEM_RD

A value of 1 specifies a read operation; 0 specifies write.

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 90 91

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