CDA CD 60 Spezifikationen PDF herunterladen (Seite 86)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 86

Stat Polarity Register

Size 8-bit

I/O read-write

Address 0x04

Access PCD_STAT_POLARITY

Bit PCD_ Description

D0-3 POLARITY A value of 0 indicates that a change from 0 to 1 from one

clock cycle to the next causes an interrupt in the

corresponding bit of the STAT_INT register, if the

corresponding bit is also enabled in STAT_INT_EN.

A value of 1 causes the same event when the STAT_INT

bit changes from 1 to 0 from one clock cycle to the next.

D4 STAT_INT_ENA Provides global enable or disable for all interrupt bits in Stat

in one operation, without altering the state of the Stat

Stat interrupts to determine which other interrupts are

pending. A value of 1 enables the interrupts.

D5 ENA_OUT_CTRL When set, enables the OUTPUT DISABLE signal on

pin 22. Not used on CDa boards.

D6-7 Not used.

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CDA CD 60 Spezifikationen Seite 86