CDA CD 60 Spezifikationen PDF herunterladen (Seite 84)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 84

Data Path Status Register

Size 8-bit

I/O read-only

Address 0x01

Access PCD_DATA_PATH_STAT

Bit EDT_ Description

D0 OF_NOT_EMP If this bit is set, the output FIFO is not empty.

D1 IF_NOT_EMP If this bit is set, the input FIFO is not empty.

D2 UNDERFLOW If the DNR signal is low and the ODV signal goes low

because the output FIFO runs out of data, this bit is

asserted and remains so throughout the data transfer.

Reset this bit with the ENABLE bit in the Command

D3 OVERFLOW This bit is asserted when the input FIFO is full and the IDV

signal is high. Reset this bit with the ENABLE bit in the

Command register.

D4-5 INFFULL If set, input FF is full.

D6 INFFAFULL If set, input FF is almost full.

D7 IDV Reflects IDV state.

Funct Register

Size 8-bit

I/O read-write

Address 0x02

Access PCD_FUNCT

Bit PCD_ Description

D0-3 FUNCT Sets the state of the user-definable FUNCT outputs.

D4-6 FREQ6

FREQ7

SELAV

PCI CD: Used to program the PLL and select clock with the

EDT library routine

edt_set_out_clock.

PCI CDa: Not used.

D7 PLLCLK Set to enable PLL.

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CDA CD 60 Spezifikationen Seite 84