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PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 56

For example, to achieve 15 MHz using a PCI CD-20 (f

xtal

= 10 MHz), the following numbers work

(although they are not unique):

N=60, V=1, M=10, R=2, H=1, L=1, X=1

To achieve 125 Hz in a PCI CD-20 (f

xtal

= 10 MHz), the following numbers work (although they are

not unique):

N=50, V=1, M=10, R=8, H=5, L=50, X=100

The output clock has a wide range of values, but the frequency limitations at different stages limits the

ultimate ability to exactly hit any specific frequency.

An example, the PLL reference frequency can be as low as 200 KHz: that would seem to allow steps of

200,000 in the VCO output. Unfortunately, since the maximum VCO output is 50 MHz and the

nprogrammable divider only goes to 127, the loop cannot lock unless V is set to 8, giving 1.6 MHz

minimum steps. Now if R is set to 8, we can get 200 KHz steps at f

xilinx

. The lowest frequency in this

case is at N=32 (6.4 MHz) to N=127 (25.4 MHz), in 200 KHz steps.

The following three library routines help compute the output clock frequency:

Routine Description

edt_find_vco_frequency Computes the phase-locked loop parameters necessary to match (or

approximate) the supplied target frequency.

edt_set_pll_clock Sets the phase-locked loop circuit to the value computed by

edt_find_vco_frequency. Includes debugging information.

edt_set_out_clock Sets the phase-locked loop circuit to the value computed by

edt_find_vco_frequency. Does not include debugging information.

Table 1. Output Clock Generation Library Routines

edt_find_vco_frequency

Description

Computes the phase-lock loop parameters described in Figure 1 that are necessary to match or

closely approximate the supplied target frequency, and builds the edt_pll structure with these

computed values. Because of the hardware constraints described in the Legend to Figure 1, the

target frequency may not be possible. This routine returns the actual frequency calculated.

Note

This routine computes the necessary values but does not set the phase-locked loop

circuit. To set the circuit, use edt_set_out_clock or edt_set_pll_clock, described next.

Syntax

#include “edtinc.h”

double edt_find_vco_frequency (EdtDev *edt_p, double target,

double xtal, edt_pll *pll, int verbose);

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