CDA CD 60 Spezifikationen PDF herunterladen (Seite 89)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 89

ragged ODV on start and underflows.

5 SETDNR A value of 1 stops transfer to device as if device set to

DNR.

6 PIOEN A value of 1 translates DMA channel buffers and enables

programmed I/O registers at 8 and 9. A write to 9

generates a 1 clock inside ODV.

7 SETIDV Set input data valid (used for debug).

PLL Programming Register (PCI CDa only)

Size 8-bit

I/O read-write

Address 0x20

Access EDT_SS_PLL_CTL

Comments The program set_ss_vco uses this register to program the serial interface

of the PLL.

Bit Name Description

3-0 PLL_STROBE Connected to the strobe inputs of PLL 3 to 0, respectively.

5-4 Not used.

6 PLL_DATA Connected to PLL serial data input.

7 PLL_SCLK Connected to PLL serial clock input.

PLL Divider Register (PCI CDa only)

Size 8-bit

I/O read-only

Address 0x24, 0x25

Access EDT_SS_PLL0_CLK, EDT_SS_PLL0_X

Comments This register is set by set_ss_vco. It is a post-scalar divider used to

achieve lower frequencies than those at which the PLLs can be programmed.

After this division, the clocks are divided by two again to even the duty cycle.

The set_ss_vco considers all these effects. Set D7 in the Funct register to

enable.

Bit Name Description

15-0 PLLDIV Programmable post divider

1 2 ... 84 85 86 87 88 89 90 91

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CDA CD 60 Spezifikationen Seite 89